简介:Time-to-DigitalConverter(TDC)isakeyblockusedasthephase/frequencydetectorinanAll-DigitalPhase-LockedLoop(ADPLL).Usually,itoccupiesalargeproportionofADPLL'stotalpowerconsumptionuptoabout30%to40%.Inthispaper,thedetailedpowerconsumptionofdifferentcomponentsintheTDCisanalyzed.APowerManagementBlock(PMB)ispresentedfortheTDCtoreduceitspowerconsumption.A24-bitsTDCcorewiththeproposedPMBisimplementedinHJTC0.18μmCMOStechnology.Simulationresultsshowthatupto84%powerreductionisachievedusingourproposedtechnique.
简介:Adigitalwatermarkingtechniqueisamulti-scientificdisciplinewhichisdevelopedrapidlyinlastseveralyearsfordigitalcontentprotection,suchascopyrightprotection,authenticationprotection,sourcetracing,etc.However,inrealisticscenarios,thedigitalwatermarkingsystemfacessignificantsecureissues,forexample,theattackerswanttoremove,detect,orembedillegalwatermarksignals.Therefore,theaimofthiscontributionistoillustraterecentresultsofrobustandsecurewatermarkingtothesignalprocessingcommunity,andhighlightbothbenefitsandstillopenissues.Specifically,thispaperisintendedtointroducetheconceptofsecureandrobustdigitalwatermarkingsystem,andprovidewithproblemsandtheircountermeasures.Firstofall,theclassicwatermarkmodelandcryptosystemwillbereviewedandthen,theconceptofsecureandrobustdigitalwatermarkingsystemwillbedescribed.Next,thewatermarkattackwillbeclassifiedanddescribed.Finally,somecountermeasuresthatcanhelptoimprovesecureandrobustnessareconsidered.IndexTermsCountermeasures,digitalwatermarkingsystem,robust,security,watermarkattacks.
简介:Arobustdigitalreceiverbasedonamatchedfilter(MF)isproposedfortheradiofrequencyidentification(RFID)readersystemtoenhancethereliabilityofsignalprocessingintheelectronicproductcode(EPC)sensornetwork(ESN).Theperformanceoftheproposedreceiverisinvestigatedbyexaminingtheanti-collisionalgorithmintheEPCglobalClasslGeneration2protocol.Thevalidityandusefulnessaredemonstratedbybothcomputersimulationsandexperiments.Basedontheverificationresults,comparingwiththeconventionalzerocrossingdetector(ZCD)basedreceiver,theproposedreceiverisveryrobustagainststrongamplitudedistortionsandconsiderablefrequencydeviationshappeningonthebackscatteredsignalfromapassivetag.
简介:Anewdigitalmodulationrecognitionalgorithmbasedontheinstantaneousinformationisproposedtoimprovetherecognitionsuccessrateinthelowsignalnoiseratio(SNR).Firstdenoisingoftheinstantaneousinformationisoptimizedbywaveletfilter,whichcanimprovetherecognitionabilityatlowSNR.Besidestheexisting3keyfeatureparameters,3newkeyfeatureparametersareproposedtobeusedasthedecisioncriteriaforidentifyingdifferenttypesofdigitalmodulation,whichsimplifiestherecognitionprocessandimprovestherecognitionabilityatlowSNR.Thesimulationsdemonstratethatallmodulationtypesofinteresthavebeenclassifiedwithsuccessrateofnolowerthan99%whenSNRis10dB.EveniftheSNRislowerthan5dB,thesuccessrateisover95.4%formostofthemodulationtypes.
简介:Atechnologyforcombiningdigitalwatermarkswithtwo-colorbitmapimageonthethresholdwatermarkingmethodispresented.Ourtechnologydoesn'taddanythingtothedigitalmedia,butcombinesthewatermarksintwo-colorbitmapimagebylookingforsomecharacteristicvaluesinthebitmapandusestherelationshipbetweenthewatermarksandthecharacteristicvaluestoprovethecopyrightprotection.Thechoiceofthecharacteristicvaluesdependsonthechoiceofacryptographickeyknownbytheownerofthebitmap.Thebenefitofusingacryptographickeyistocomginethewatermarkswiththebitmapinahighsecureway.
简介:一个新奇optical-spectrum-encoded(OSE)analog-to-digital变换器(模数转换器)在这个字母被建议。简单地例示变换想法,5位的设备结构由Fabry-Perot干涉仪(FPI)组成了被分析并且数字地模仿了。在电镀物品光的FPI的调整电压上的山峰传播波长的依赖和在FPI的事件光波长上的播送功率的依赖被讨论并且利用了实现OSEADC。线性地悦耳的锁模式的激光作为一个电压波长变压器和一个刺绣花样,并且作为一个编码器数组,啁啾的栅栏FPI能被用来获得许多更大的采样率和小点决定。CLC数字TH867+.91
简介:AnapproachisproposedtorealizeadigitalchannelizedreceiverinthefractionalFourierdomain(FRFD)forsignalinterceptapplications.ThepresentedarchitecturecanbeconsideredasageneralizationofthatinthetraditionalFourierdomain.Sincethelinearfrequencymodulation(LFM)signalhasagoodenergyconcentrationintheFRFD,bychoosinganappropriatefractionalFouriertransform(FRFT)order,thepresentedarchitecturecanconcentratethebroadbandLFMsignalintoonlyonesub-channelandthatwillpreventitfromcrossingseveralsub-channels.Thustheperformanceofthesignaldetectionandparameterestimationafterthesub-channeloutputwillbeimprovedsignificantly.Thecomputationalcomplexityisreducedenormouslyduetotheimplementationofthepolyphasefilterbankdecomposition,thustheproposedarchitecturecanberealizedasefficientlyasintheFourierdomain.Therelatedsimulationresultsarepresentedtoverifythevalidityofthetheoriesandmethodsinvolvedinthispaper.
简介:Digitalcircuitsoperatinginthesub-thresholdregimeconsumetheleastenergy.Thestrictenergyconstraintsaredesiredintheapplicationswhichworkatthelowestpossiblesupplyvoltage.Ontheotherhand,theconventionaldesignflowutilizesthetechnologylibraryprovidedbythefoundrywithafixedvoltageboundary,whichcausesproblemswhenthesupplyscalesdowntothesub-thresholdregime.Inthispaper,wepresentadesignmethodologytocharacterizetheexistingcelllibrarywithLibertyNCXtofacilitatethestandarddesignflow.Itisdemonstratedin0.13mcomplementarymetal-oxide-semiconductor(CMOS)technologywiththesupplyvoltageof300mV.
简介:Thewide-banddigitalreceivingsystemsrequiredigitaldownconversion(DDC)withhighdatarateandshorttuningtimeinordertointerceptthenarrow-bandsignalswithinbroadtuningbandwidth.ButtheserequirementscannotbemetbythecommercialDDC.Inthispaperanefficientimplementationarchitectureispresented.ItcombinestheflexibilityofDFTtuningwiththeefficiencyofthepolyphasefilterbankdecomposition.Byfirstdecimatingthedatapriortofilteringandmixing,thisarchitecturegivesabettersolutiontothemismatchbetweenthelowerhardwarespeedandhighdatarate.Thecomputersimulationsshowthefeasibilityofthisprocessingarchitecture.
简介:Thesolarphotovoltaic(PV)moduleoutputvoltagechangesaccordingtothevariationoflightintensityandtemperature.ThispaperpresentstheimplementationofanautomaticdigitalcontrollerofaDC-DCboostconverterwithoutbatteriesforasolarcellmodulebyusingaperipheralinterfacecontroller,whichformsaclosedloop,tocontroltheON-OFFperiodoftheswitchingpulse.TheoutputofDC-DCconverterismaintainedbyautomaticallyincreasingordecreasingthepulsewidth.Toproducethepulsewidthmodulation(PWM),themicrocontrollerisprogrammedaccordingtotherequireddutycycleforthepowerswitch.ThePWMONperiodisincreasedwiththedecreaseinthePVvoltageandvice-versa.TheinputvoltagetotheinverterismaintainedconstantlyandisconvertedintoanACsignalbyusingthemetal-oxide-semiconductorfieldeffecttransistor(MOSFET)H-bridgeoperatedinthesinusoidalpulsewidthmodulationmodebyusingaPIC(peripheralinterfacecontroller)microcontroller.ThegeneratedACsignalcanbeconnectedtotheACgridortotheACload.ThesimulatedresultsbyusingProteus8andhardwareimplementedresultsverifytheeffectivenessoftheproposedcontroller.
简介:Inthispaper,thecloserelationshipamongwavelettransformandquadraturemirrorfilter(QMF)banksandthescattering-matrixofwavedigitalfilter(WDF)isandlyzedindetail.TheparametrizationoforthonormalcompactlysupportedwaveletbasesthathaveanarbitrarynumberofvanishingmomentisobtainedbybuildinganyQMFpairoutofelementaryfactorsofthescatteringmatrix.Inaddition,theoptimizationofparameterisalsopresented.Ascomparison,Someexamplesaboutorthonormalcompactlysupportedwaveletthathasarbitrarynumberofvanishingmomentandthemostnumberofvanishingmomentaregivenrespectively.Thenwegivetheefficientlatticestructuretoimplementthetransform.
简介:Twosignaturesystemsbasedonsmartcardsandfingerprintfeaturesareproposed.Inonesignaturesystem,thecryptographickeyisstoredinthesmartcardandisonlyaccessiblewhenthesigner'sextractedfingerprintfeaturesmatchhisstoredtemplate.Toresistbeingtamperedonpublicchannel,theuser'smessageandthesignedmessageareencryptedbythesigner'spublickeyandtheuser'spublickey,respectively.Intheothersignaturesystem,thekeysaregeneratedbycombiningthesigner'sfingerprintfeatures,checkbits,andarememberablekey,andtherearenomatchingprocessandkeysstoredonthesmartcard.Additionally,thereisgenerallymorethanonepublickeyinthissystem,thatis,thereexistsomepseudopublickeysexceptarealone.
简介:AkindofarchitectureofTime-to-DigitalConverter(TDC)forUltra-WideBand(UWB)applicationispresented.TheproposedTDCisbasedonpulseshrinking,andimplementedinaFieldProgrammableGateArray(FPGA)device.ThepulseshrinkingisrealizedinaloopcontainingtwoProgrammableDelayLines(PDLs)oratwo-channelPDL.Oneline(channel)delaystherisingedgeandtheotherline(channel)delaysthefallingedgeofacirculatingpulse.DelayresolutionofPDLisconvertedintoadigitaloutputcodeunderknownconditionsofpulsewidth.Thisdelayresolutionmeasurementmechanismisdifferentfromtheconventionaltimeintervalmeasurementmechanismbasedonpulseshrinkingofconversionofunknownpulsewidthintoadigitaloutputcode.Thismechanismautomaticallyavoidstheinfluenceofunwantedpulseshrinkingbyanycircuitelementapartfromthelines.TheachievedrelativeerrorsforfourPDLsarewithin0.80%–1.60%.