A LOW POWER TIME-TO-DIGITAL CONVERTER FOR ALL-DIGITAL PHASE-LOCKED LOOP-中国期刊网

摘要 Time-to-DigitalConverter(TDC)isakeyblockusedasthephase/frequencydetectorinanAll-DigitalPhase-LockedLoop(ADPLL).Usually,itoccupiesalargeproportionofADPLL'stotalpowerconsumptionuptoabout30%to40%.Inthispaper,thedetailedpowerconsumptionofdifferentcomponentsintheTDCisanalyzed.APowerManagementBlock(PMB)ispresentedfortheTDCtoreduceitspowerconsumption.A24-bitsTDCcorewiththeproposedPMBisimplementedinHJTC0.18μmCMOStechnology.Simulationresultsshowthatupto84%powerreductionisachievedusingourproposedtechnique.

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A LOW POWER TIME-TO-DIGITAL CONVERTER FOR ALL-DIGITAL PHASE-LOCKED LOOP

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A LOW POWER TIME-TO-DIGITAL CONVERTER FOR ALL-DIGITAL PHASE-LOCKED LOOP

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